1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a programmable logic device for use in the former, the semiconductor integrated circuit including a master mode programmable logic device and at least one slave mode programmable logic device disposed downstream of the master mode logic device and having a logical function thereof defined by configuration data inputted thereinto from the master mode logic device or an upstream slave mode logic device through a data line, and more sepecifically to a semiconductor integrated circuit or a programmable logic device for use in the former which eliminates use of a pulse counter which is to count a sync. clock supplied from a master mode logic device to a slave mode logic device when logical function configuration data is transferred and supplied from an external memory through a programmable logic device in a master mode to a programmable logic device in a slave mode, and interrupt the sync. clock upon the data transfer is completed.
2. Description of the Prior Art
In a programmable logic device, say, a programmable gate array, which has a logical function specified by configuration data inputted from an external memory such as a ROM and an EPROM, etc., it is necessary to define the logical function by supplying logical function configuration data to each programmable logic device prior to use thereof.
It is therefore prior practice as illustrated in FIG. 10 for instance that a plurality of (n+1 in the figure) programmable logic devices are connected in series to each other, a most upstream programmable logic device among which is defined a programmable logic device 10a in a master mode (hereinafter, referred to as a master logic device) to which a read only memory (ROM) 20 that stores therein logical function configuration data of each programmable logic device is connected. Alternatively, n programmable logic devices 10b in a slave mode, for example, of the same hardware as that of the foregoing master logic device 10a, slaved to the same are connected to the foregoing master logic device 10a in series.
For loading the logical function configuration data, the master logic device 10a outputs an address from an address counter 11 thereof to the ROM 20 which then outputs configuration data of 8 bits for example corresponding to that address. On the basis of the configuration data master data is first stored in a circuit configuration memory 12 of the master logic device 10a, and then slave data is outputted from an output terminal Dout of the master logic device 10a and inputted into an input terminal Din of a downstream slave logic device 10b, and further transferred to successive slave logic devices in the order of from slave No. 1 to No. n and stored in those slave logic devices. In other words, the logic devices 10b serving as slaves other than the master logic device 10a receive the logical function configuration data from the ROM 20 through the master logic device 10a. Herein, after completion of the configuration mode, the operation enters a use mode.
The master logic device 10a therefore has a need of supplying a sync. clock CCLK for determining data incorporation timing to each slave logic device 10b in order to enable each slave logic device 10b to accurately receive the configuration data, and of counting the total clock number until the logical function configuration data is transferred to all slave logic devices 10b to take synchronism upon the configuration for all logic devices being completed, and further of, after the configuration data is stored in circuit configuration memory 12 of all programmable logic devices, interrupting the sync. clock CCLK to complete the configuration mode and enter the use mode.
For this reason, conventionally, in a system including a plurality of the programmable logic devices, each programmable logic device incorporates a pulse counter 16 therein besides a pulse generator (PG) 14 to control the generation of the synchronizing clock CCLK pulse by writing in the configuration data for the master logic device 10a the number of generated pulses of the synchronizing clock CCLK corresponding to the total data number for loading the configuration data from the ROM 20 to the whole system.
In such a system, however, each programmable logic device is inevitably required to incorporate therein the pulse counter 16 and each slave logic device 10b is also required to include the same pulse counter as that in the master logic device 10a, resulting in a disadvantage of a system area being increased to prevent the system from being integrated. Additionally, since the total configuration data number of the system is determined by the size of the pulse counter 16, for systems large-sized to some extent in which many programmable logic devices operate, the pulse counter 16 is obliged to be one of a relatively large size. Alternatively, in a small-sized system in which there is no need of use of a plurality of programmable logic devices, the pulse counter 16 is quite wasteful, resulting in the increased chip cost and lowered yield.